Loop Scheduling Algorithm for Timing and Memory Operation Minimization with Register Constraint

Loop pipelining is a scheduling technique widely used to improve the performance of systems running scientiic applications, such as multimedia and DSP systems. These applications usually contain repetitive groups of operations represented by nested loops, categorized by multi-dimensional systems. Considerable research has been conducted to produce high throughput schedules under resource constraint. Nevertheless, unlimited number of registers were assumed in these studies. In this paper, we present a novel scheduling framework, called Memory Operation minimization Rotation Scheduling (MORS), for scheduling multi-dimensional applications under register constraint and other resource constraint. Keeping on satisfying the register constraint , MORS incrementally compacts the schedule to achieve a high throughput schedule. Moreover, this methodology strives to shorten the schedule length while minimally inserting the load and store operations in the schedule to reduce the register requirement pressure. Experiments show that our approach is useful for reducing the schedule length without violation the register constraint in multi-dimensional systems. The average reduction in schedule length of our experiments reaches 36.2%.